System and method to avoid voltage read errors in open digit line array dynamic random access memories

ABSTRACT

Selective coupling devices directed by coupling controllers prevent cell plate and/or substrate disturbances from causing memory cell read and refresh errors in open digit line array memory devices. Using selective decoupling devices, when memory cells in an active row store an appreciably unbalanced number of either zeroes or ones, reading the cells generates a voltage transient in the cell plate and/or substrate that can be coupled to a reference digit line because the cell plates and/or substrates of the active sub-array are normally coupled to the cell plates and/or substrates of the reference arrays. By decoupling the cell plate and/or substrate of the active sub-array from the cell plates and/or substrates of the reference arrays, any coupling of the voltage transients to reference digit lines is reduced.

TECHNICAL FIELD

[0001] This invention relates to DRAM devices. More particularly, thepresent invention is directed to DRAM devices employing open digit linearray architecture.

BACKGROUND OF THE INVENTION

[0002] As is well known in the art and shown in FIG. 1, a DRAM cell 100typically comprise a capacitor 104 and access transistor 108 pair. Oneplate of the capacitor 104 is connected to a common cell plate (notshown) to which all capacitors in that DRAM cell array are connected, asubset of which 112 is shown in FIG. 1. The other plate of the capacitor104 is coupled to a drain of the access transistor 108. The gate of theaccess transistor 108 is connected to a word line 116 which allows allthe DRAM cells coupled to each word line 116 to be activated, while thesource of the access transistor 108 is coupled to a digit line 120 whichthe DRAM cell 100 will read from and write to during memory operations.Activating the gate of the access transistor allows a high voltagecharge (Vcc) or low voltage charge (ground) carried by the digit line120 to pass to the capacitor 104, thus writing the voltage of the digitline 120 to the capacitor 104.

[0003] DRAM cell storage technology of this type is understandablytransitory in nature: the high or low voltage charge written to thecapacitor will eventually dissipate, as charges stored across capacitorsare known to do. As also is known in the art, stored charges leak acrossthe dielectric core between the transistor plates, and voltages can leakfrom the plates through the access transistors to which they areconnected. As a result, the contents of DRAM cells typically must berefreshed hundreds of times per second.

[0004] A network of sense amplifiers 124 (FIG. 1) typically are used torefresh the contents of the DRAM cells, each of the sense amplifiers 124comparing voltages received on pairs of digit lines 120 to which each isconnected.

[0005] The memory cells 100 are shown in FIG. 1 arranged in an opendigit line configuration in which each sense amplifier 124 is coupled toa column of memory cells in one array 125 and another column of memorycells in another memory array 126. Each pair of digit lines 120 to whicheach sense amplifier 124 is connected comprises an active digit line anda reference digit line. The active digit line 128 is the digit line inone array 125 to which the access transistors 108 of the DRAM cells 100being refreshed are coupled upon activation of the word lines 116activating the gates of the access transistors 108. The active digitline is assumed to be the top digit line 128 in the array 125 forpurposes of the example of FIG. 1. The reference digit line 132 is adigit line connected to a row of DRAM cells 100 whose contents will notbe refreshed during the refresh cycle and is assumed to be the digitline 132 in the array 126 for purposes of the example of FIG. 1. Priorto the refresh cycle, both the active digit line 128 and reference digitlines 132 are equilibrated by precharging the digit lines 120 to Vcc/2so that the sense amplifiers 124 can measure the voltage disparitybetween them.

[0006] When the access transistors 108 of the DRAM cells 100 coupled tothe active digit line 132 and the sense amplifiers 124 are activated,each of the sense amplifiers 124 determines which of the two digit lines120 carries the higher voltage and the lower voltage, and then drivesthe higher voltage digit line toward Vcc and the lower voltage digitline toward ground. Thus, when the row of DRAM cells 100 coupled to theactive digit line 128 is activated, each of these DRAM cells 100 storinga high voltage charge, even allowing for leakage which necessitatesthese refresh cycles, should carry a voltage of something greater thanVcc/2. Similarly, DRAM cells 100 storing a low voltage charge, allowingfor leakage, should carry a voltage of less than Vcc/2. Ideally,therefore, the sense amplifiers drive the DRAM cell 100 coupled to eachof the active digit lines toward Vcc or ground, whichever voltage wasstored in the DRAM cell 100 before it was refreshed.

[0007] However, conditions are not always ideal. For example, dependingupon the combinations of charges stored in the DRAM cells 100 coupled tothe active digit lines 128, the sense amplifiers 124 might notaccurately read the charges on the DRAM cells 100 coupled to the activedigit lines 124. For example, if a capacitor 104 of a DRAM cells 100stores a high voltage charge, but, for some reason, the voltage read bythe sense amplifier 124 appears to be below the equilibrated Vcc/2 valueof the reference digit line 132, the sense amplifier 124 will drive theactive digit line 132 toward ground, refreshing the previously highvoltage charge carrying DRAM cell to 100 a low voltage state, corruptingdata.

[0008] One way this can happen is through voltage fluctuations or noiseaffecting digit lines to which a sense amplifier 124 is coupled. Morespecifically, since the active digit line 128 extends though one array125 and the reference digit line 132 extends through a different array126, the active digit line 128 and the reference digit lines 132 can beexposed to different noise sources. Noise signals coupled to one of thedigit lines 128 or 132 but not the other 132 or 128 can cause the senseamplifiers 124 to sense an erroneous voltage level. The manner in whichnoise signals can be coupled to the active digit line 128 and thereference digit line 132 will be discussed in greater detail below.

[0009] As mentioned earlier, differential noise coupled to the digitlines 128, 132 is a problem with the open digit line architecture shownin FIG. 1 primarily because the active digit line 128 and the referencedigit line 132 extend through different arrays 125, 126, respectively.In contrast, an array 250 having a folded digit line architecture shownin FIG. 2A does not have this problem. The folded digit line array 250includes a sense amplifier 262 coupled to respective complimentary pairsof digit lines 258 provided for each column 266 of memory cells 254.Each digit line 258 is connected to alternate memory cells 254 in eachcolumn 266. For each read or write operation, one of the digit lines 258in each pair serves as the active digit line and the other digit line258 in the pair serves as the reference digit line. Thus, instead ofextending through different arrays as in an open digit linearchitecture, active and reference digit lines 258 having a foldedarchitecture extend through the same array 250 in close proximity witheach other. As a result, arrays 250 having a folded digit linearchitecture have good common mode noise rejection since the active andreference digit lines 258 are exposed to the same noise sources tosubstantially the same degree.

[0010] Although a folded digit line architecture provided good commonmode noise immunity, it has the disadvantage of consuming more area on asemiconductor die (not shown) compared to an open digit linearchitecture, which is shown in FIG. 2B. As is well known in the art,each memory cell in an open digit line architecture requires only 4F² or6F² in area, where F represents the feature size, whereas each memorycell 254 in a folded digit line architecture requires 8F² in area. Thissignificant disparity allows memory devices using an open digit linearchitecture to consume substantially less space on a semiconductor dieso that such memory device can be substantially cheaper than memorydevices using a folded digit line architecture.

[0011]FIG. 2B shows two open digit line sub-arrays 200 and 202. Digitlines 203, 204 connected to each sense amplifier 206 in the open digitline sub-arrays 200 and 202 are not connected to memory cells 208 in thesame sub-array. Instead, each sense amplifier 206 is connected to onedigit line 203 in one sub-array 200 and one digit line 204 in a secondsub-array 202. Each sub-array 200, 202 has its own cell plate 210, 212,respectively coupled to the memory cell capacitors in its respectivesub-array 200, 202. Furthermore, each sub-array 200, 202 is oftenfabricated in separate semiconductor wells that form separate substrates214, 215 that are isolated from each other, such as by using a “triplewell” structure, which is known in the art. As will be appreciated, thedigit lines 203 in the first sub-array 200 can be exposed to differencenoise sources than the noise sources to which the digit lines 204 in thesecond sub-array are exposed. Noise can be coupled to the digit lines203, 204 differently for several reasons. For example, because the digitlines 203, 204 in the different sub-arrays 200, 202 are fabricated indifferent substrates, noise signals generated in the substrates can becoupled to the digit lines 203, 204. Differential noise can also resultfrom noise signals coupled to differently to the cell plates 210, 212 ineach sub-array 200, 202, respectively.

[0012] Various approaches have been used to improve the noise immunityof memory devices using an open digit line architecture. One approachhas been to couple corresponding nodes in the sub-arrays 200, 202 toeach other so that a voltage disturbance or noise in one of the nodeswill also occur in the corresponding node. As a result, if the voltagedisturbance or noise is coupled from the node to a digit line in onearray, the voltage disturbance will, in theory, also be coupled from thecorresponding node to the corresponding digit line in the other array.For example, as shown in FIG. 2B, the cell plate 210 of the firstsub-array 200 and the cell plate 212 of the second sub-array 202 areelectrically connected by a conductive coupling 217. Theoretically, thismeasure should alleviate uneven cell plate disturbances by bringing allthe coupled cell plates to the same voltage. Similarly, a conductor 219is used to couple the substrate 214 in which one sub-array 200 isfabricated to the substrate 215 in which the other array 202 isfabricated. Although these conductive couplings 217, 219, as well asother conductors (not shown) coupling corresponding nodes to each other,do, in fact, improve the noise immunity of the sub-arrays 200, 202 insome cases, they can actually creates noise problems that have veryadverse consequences, as will be explained below.

[0013] With further reference to FIG. 2B, assume that one of the memorycell capacitors 216 in the sub-array 200 is storing a high voltage,e.g., V_(CC), and all of the other memory cell capacitors in thesub-array 200 are storing a low voltage, e.g., ground potential. This isknown as a “1 in a sea of zeros” situation. The capacitor 216 and all ofthe other capacitors in the sub-array 200 are coupled to the same cellplate 210. As previously explained, the digit lines 203 in the sub-array200 are equilibrated to one-half the supply voltage, ie., V_(CC)/2,prior to a memory read operation. Assuming that the sub-array 200 is anactive arrays when the access transistors 203 are activated for thememory cells 208 storing a 0, the voltage on each of the capacitorplates in such memory cells quickly transition from 0 volts to theequilibrated voltage V_(CC)/2 of the digit lines. The sudden increase involtage coupled to all of the memory cell capacitors except for thecapacitor 216 causes the voltage of the cell plate 210 to also increase.The voltage increase on the cell plate 210 is also coupled to the memorycell capacitor 216, which has a plate that has been charged to V_(CC).

[0014] The cell plate 210 is also coupled to the capacitor 104 of thelone cell 216 storing a 1. As a result, the cell plate 210 will tend todrive the voltage stored in the capacitor 216 higher as well. This makesit more likely that the sense amplifier 206 will correctly sense thevoltage on the capacitor 216 as corresponding to a 1. However, becausethe cell plate 210 of the sub-array 200 is also coupled to the cellplate 212 of the array 202, the voltage on the cell plate 212 alsoincreases. This increase in voltage of the cell plate 212 can becapacitively coupled to the reference digit line 204 in the array 202.In fact, the voltage disturbance on the cell plate 210 can be coupled tothe reference digit line 204 with an even greater magnitude than it iscoupled to the active digit line 203, partly because any voltageincrease in the active digit line 203 is coupled to the capacitor 216,which somewhat acts as a low-pass filter. Thus, the conductor 217provided to couple the cell plates 210, 212 to each other for thepurpose of reducing data read errors, can actually increase data readerrors. Similarly, the conductor 219 coupling of the substrates 214, 215for the sub-arrays 200, 202, respectively, to each other can alsoincrease rather than decrease memory read errors.

[0015] In an open digit line array architecture device, the types ofcell plate and semiconductor substrate disturbances previously describedcould be overcome by refreshing the memory cells more often. After all,if memory cells were refreshed before the voltages they storeddissipated so as to closely approach Vcc/2, the type of voltagedisturbances previously discussed would no longer pose a problem. On theother hand, refreshing memory cells consumes appreciable amounts ofpower, and it is desirable to reduce power consumption in memory devicesto avoid generation of waste heat and, more importantly, to help prolongbattery life in portable devices.

[0016] There is therefore a need for a circuit and method that canobtain the size advantages of an open digit line architecture withoutincurring the power consumption costs typically incurred by the higherrefresh rates needed for memory devices using an open digit linearchitecture.

SUMMARY OF THE INVENTION

[0017] The present invention is directed to a system and method forselectively coupling and decoupling sub-arrays in open digit line arraymemory devices to prevent cell late and semiconductor substratedisturbances from causing memory cell read and refresh errors. Inparticular, the present invention exploits the fact that, when thememory cells in a sub-array store an appreciably unbalanced number ofeither zeroes or ones, the nominal voltages of the cell plate and/orsubstrate for the sub-array undergo transient changes that can result indata read errors. More specifically, in an open digit line architecture,the present invention couples cell plates and/or substrates to the cellplates and/or substrates, respectively, between adjacent arrays to allowfor the equalization of cell plate and/or substrate voltages up untilthe equilibrated active digit lines are to be coupled to the memorycells to read and/or refreshed the memory cells. The cell plate and/orsubstrate for the active sub-array are then decoupled from the cellplate and/or substrate of the reference sub-arrays to reduce thecoupling of any voltage transient in the cell plate and/or substrate ofthe active sub-array to the cell plate and/or substrate of the referencesub-arrays.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a schematic diagram of portions of conventionalsub-arrays of DRAM memory cells having an open digit line architecture.

[0019]FIGS. 2B2A is a schematic diagram of a conventional foldeddigit-line-digit line array architecture sub-array.

[0020]FIG. 2B is a schematic diagram of a pair of conventional opendigit line array architecture sub-arrays with coupled cell plates andsubstrates.

[0021]FIG. 3A is a block diagram of a first embodiment of the presentinvention featuring cell plate decoupling devices and control logic toselectively decouple an active sub-array from a reference sub-array.

[0022]FIG. 3B is a block diagram of a second embodiment of the presentinvention featuring cell plate decoupling devices and control logic toselectively decouple an active sub-array from other sub-arrays.

[0023]FIG. 4 is a block diagram of a SDRAM device incorporating anembodiment of the present invention.

[0024]FIG. 5 is a block diagram of a computer system incorporating anembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0025]FIG. 3A is a block diagram of a selective cell plate couplingsystem 300 for selectively coupling cell plates of adjacent sub-arraysto each other in an open digit line architecture. FIG. 3A shows Nsub-arrays, namely sub-array 302(1), sub-array 302(2), sub-array 302(3).The sub-arrays 302 designated by an odd number in parentheses arecoupled to odd-numbered word lines (not shown) and the sub-arrays 302designated by an even number in parentheses are coupled to even-numberedword lines (not shown). Thus, when even numbered word lines areactivated, one or more of the even-numbered arrays function as activearrays and the adjacent odd-numbered arrays function as referencearrays. Similarly, when odd numbered word lines are activated, one ormore of the odd-numbered arrays function as active arrays and theadjacent even-numbered arrays function as reference arrays. A pluralityof sense amplifiers 308 are used to read memory cells (not shown in FIG.3A) coupled to respective active digit lines by comparing them withrespective reference digit lines. The capacitors of the memory cells(not shown) in each sub-array 302 are coupled to individual sub-arraycell plates 310(1), 310(2), and 310(3). This much of the system 300 isconventional and known in the art.

[0026] Added to this system is a selective cell plate couplingtransistor 330 which is coupled to a controller 332. The transistor 330has one of its terminals coupled through signal line 334 to all of theodd-numbered sub-arrays 302 and the other of its terminals coupledthrough signal line 336 to all of the even-numbered sub-arrays 302. Thecontroller 332 receives signals generated by other circuitry in a DRAMproviding an indication of when a memory read operation is to occur,such as from a row active line 337. The controller 332 normally appliesa signal to the gate of the transistor 330 to turn ON the transistor330. The transistor 330 and signal lines 334, 336 then couple the cellplates 310 of all of the odd-numbered sub-arrays 302 to the cell plates310 of all of the even-numbered sub-arrays 302. Thus, in this condition,the cell plates of adjacent sub-arrays 302 are coupled to each other. AV_(CC)/2 generator 338 is coupled to the signal line 336 to bias thecell plates 310 of the even sub-arrays 302 to V_(CC)/2. Of course, whenthe transistor 330 is ON, the V_(CC)/2 generator 338 is also coupled tothe signal line 334 to bias the cell plates 310 of the odd sub-arrays302 to V_(CC)/2. The large capacitance of the cell plates 310 allows thevoltage of the cell plates 310 for the odd-numbered sub-arrays 302 toremain essentially constant at V_(CC)/2 .

[0027] In operation, the controller 332 maintains the transistor 330 ONso that the sub-arrays 302 operate in a convention manner, as describedabove. When a memory read is to occur, the controller 332 outputs asignal that turns OFF the transistor 330. The transistor 330 thenisolates the cell plates 310 of all of the even-numbered sub-arrays 302from the cell plates 310 for all of the odd-numbered sub-arrays 302. Indoing so, the transistor 330 isolates the cell plate 310 for eachsub-array 302 from the the cell plates 310 for adjacent sub-arrays 302.Therefore, the cell plate 310 for the active sub-array 302 is alwaysisolated from the cell plate 310 for the reference sub-arrays 302. Forthis reason, any coupling of a transient voltage in the cell plate 310for the active sub-array 302 to a reference digit line (not shown) willhave a relatively low magnitude.

[0028]FIG. 3B shows another embodiment of the invention in which asystem 340 is used to selectively couple the substrates of adjacentarrays to each other. More specifically, each of the sub-arrays 302 isfabricated in a substrate 342. The substrates 342 for the odd-numbersub-arrays 302 are coupled to a first signal line 346 and the substrates342 for the even-numbered sub-arrays 302 are coupled to a second signalline 348. The remainder of the system 340 is identical to the system 300of FIG. 3A and it operates in the same manner except that a substratebias generator 350 is used in the system 340 in place of the V_(CC)/2generator used in the system 300. The substrate bias generator 350biases the substrates 342 for the sub-arrays 302 at a suitable biasvoltage, such as zero volts or a slight negative voltage, as is wellknown in the art.

[0029] In operation, the controller 332 maintains the transistor 330 ONduring normal operation so that the substrates of all of the sub-arrays302 are coupled to each other and to the substrate bias generator 350.When a memory read is to occur, the controller 332 outputs a signal thatturns OFF the transistor 330. The transistor 330 then isolates thesubstrates 342 for all of the even-numbered sub-arrays 302 from thesubstrates 342 for all of the odd-numbered sub-arrays 302. In doing so,the transistor 330 isolates the substrate 342 for each sub-array 302from the substrates 342 for the adjacent sub-arrays 302. Therefore, thesubstrate 342 for the active sub-array 302 is always isolated from thesubstrates 342 for for the reference sub-arrays 302. Any coupling of atransient voltage in the substrate 342 for the active sub-array 302 to areference digit line (not shown) will therefore have a relatively lowmagnitude.

[0030] The system 300 shown in FIG. 3B for selectively coupling cellplates 310 to each other and the system 340 for selectively couplingsubstrates 342 to each other may be used individually or in combinationwith each other.

[0031] A memory device employing an embodiment of the present inventionis shown in FIG. 4. The memory device shown in FIG. 4 is a synchronousdynamic random access memory (“SDRAM”) device 400, although embodimentsof the present invention may be used in other DRAMs and other memorydevices. The SDRAM device 400 includes an address register 412 thatreceives either a row address or a column address on an address bus 414.The address bus 414 is generally coupled to a memory controller (notshown). Typically, a row address is initially received by the addressregister 412 and applied to a row address multiplexer 418. The rowaddress multiplexer 418 couples the row address to a number ofcomponents associated with either of two memory arrays 400 a, 400 b,depending upon the state of a bank address bit forming part of the rowaddress. The memory arrays 400 a, 400 b have an open-array architectureincorporating one or both embodiments of the invention as shown in FIGS.3A and 3B. Associated with each of the memory arrays 400 a, 400 b is arespective row address latch 426, which stores the row address, and arow decoder 428, which applies various signals to its respective memoryarray 400 a or 400 b as a function of the stored row address. The rowaddress multiplexer 418 also couples row addresses to the row addresslatches 426 for the purpose of refreshing the memory cells in the memoryarrays 400 a, 400 b. The row addresses are generated for refreshpurposes by a refresh counter 430, which is controlled by a refreshcontroller 432.

[0032] After the row address has been applied to the address register412 and stored in one of the row address latches 426, a column addressis applied to the address register 412. The address register 412 couplesthe column address to a column address latch 440. Depending on theoperating mode of the SDRAM device 400, the column address is eithercoupled through a burst counter 442 to a column address buffer 444, orto the burst counter 442, which applies a sequence of column addressesto the column address buffer 444 starting at the column address that isstored in the column-address latch. In either case, the column addressbuffer 444 applies a column address to a column decoder 448, whichapplies various column signals to respective sense amplifiers andassociated column circuitry 450, 452 for the respective memory arrays400 a, 400 b.

[0033] Data to be read from one of the memory arrays 400 a, 400 b arecoupled to the column circuitry 450, 452 for one of the memory arrays400 a, 400 b, respectively. The data are then coupled to a data outputregister 456, which applies the data to a data bus 458. Data to bewritten to one of the memory arrays 400 a, 400 b are coupled from thedata bus 458 through a data input register 460 to the column circuitry450, 452 and then are transferred to one of the memory arrays 400 a, 400b, respectively. A mask register 464 may be used to selectively alterthe flow of data into and out of the column circuitry 450, 452, such asby selectively masking data to be read from the memory arrays 400 a, 400b.

[0034] The above-described operation of the SDRAM 400 is controlled by acommand decoder 468 responsive to high level command signals received ona control bus 470. These high level command signals, which are typicallygenerated by a memory controller (not shown), are a clock enable signalCKE*, a clock signal CLK, a chip select signal CS*, a write enablesignal WE*, a column address strobe signal CAS*, and a row addressstrobe signal RAS*, with the “*” designating the signal as active low orcomplement. The command decoder 468 generates a sequence of controlsignals responsive to the high level command signals to carry out thefunction (e.g., a read or a write) designated by each of the high levelcommand signals. These control signals, and the manner in which theyaccomplish their respective functions, are conventional. Therefore, inthe interest of brevity, a further explanation of these control signalswill be transmitted.

[0035] As shown in FIG. 5, a computer system 500 can take advantage ofan embodiment of the present invention by incorporating in its systemmemory 502 DRAM devices adapted with one or both embodiments of thepresent invention as previously described. With reference to FIG. 5, acomputer system 500 includes the system memory 502 and a processor 504for performing various functions, such as performing specificcalculations or tasks. In addition, the computer system 500 includes oneor more input devices 506, such as a keyboard or a mouse, coupled to theprocessor 504 through a system controller 508 and a system bus 510 toallow an operator to interface with the computer system 500. Typically,the computer system 500 also includes one or more output devices 512coupled to the processor 504, such output devices typically being aprinter or a video terminal. One or more data storage devices 514 arealso typically coupled to the processor 502 through the systemcontroller 508 to store data or retrieve data from external storagemedia (not shown). Examples of typical data storage devices 514 includehard and floppy disks, tape cassettes, and compact disk read-onlymemories (CD-ROMs). The system memory 502 is coupled directly (notshown) to the processor 504 or to the system controller 508 to allowdata to be written to and read from the system memory 502. The computersystem 500 may also include a cache memory 522 coupled to the processor502 through a processor bus 520 to provide for the rapid storage andreading of data and/or instructions, as is well known in the art.

[0036] From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. For example, it will beappreciated that many variations can be applied to the embodiments shownwithin the broad concepts of the present invention. Accordingly, theinvention is not limited except as by the appended claims.

1. A voltage reading enhancement system for an open digit line arrayDRAM device comprising a plurality of sub-arrays, the voltage readingenhancement system comprising: a selective coupling device selectivelyelectrically coupling a component of an active sub-array to acorresponding component of a reference sub-array; and a controllercoupled with the selective coupling device and operable to receive anactive row signal, the active row signal indicating an active row ofmemory cells within the active sub-array is to be coupled with an activedigit line, the controller being responsive to the active row signal todirect the selective coupling device to decouple the component in theactive sub-array from the corresponding component in the referencesub-array when the active row signal is received.
 2. The voltage readingenhancement system of claim 1 wherein the component of the activesub-array comprises a cell plate of the active sub-array, and whereinthe corresponding component of the reference sub-array comprises a cellplate of the reference sub-array.
 3. The voltage reading enhancementsystem of claim 1 wherein the component of the active sub-arraycomprises a substrate of the active sub-array, and wherein thecorresponding component of the reference sub-array comprises a substrateof the reference sub-array.
 4. The voltage reading enhancement system ofclaim 1 wherein the selective coupling device is a transistor thecontroller selectively causes to conduct when memory cells are not beingread and selectively not to conduct when the memory cells are beingread.
 5. The voltage reading enhancement system of claim 1 wherein thecontroller is responsive to direct the selective coupling device torecouple the component in the active sub-array to the correspondingcomponent in the reference sub-array when the active row signal is notreceived.
 6. A voltage reading enhancement system for an open digit linearray DRAM device comprising a plurality of sub-arrays, the voltagereading enhancement system comprising: a selective coupling deviceselectively electrically coupling a cell plate of an active sub-array toa corresponding cell plate of a reference sub-array; and a controllercoupled with the selective coupling device and operable to receive anactive row signal, the active row signal indicating an active row ofmemory cells within the active sub-array is to be coupled with an activedigit line, the controller being responsive to the active row signal todirect the selective coupling device to decouple the cell plate in theactive sub-array from the corresponding cell plate in the referencesub-array when the active row signal is received.
 7. The voltage readingenhancement system of claim 6 further comprising a second selectivecoupling device selectively electrically coupling a substrate of theactive sub-array to a corresponding substrate of the referencesub-array.
 8. The voltage reading enhancement system of claim 6 whereinthe selective coupling device is a transistor the controller selectivelycauses to conduct when memory cells are not being read and selectivelynot to conduct when the memory cells are being read.
 9. The voltagereading enhancement system of claim 7 wherein the second selectivecoupling device is a transistor the controller selectively causes toconduct when memory cells are not being read and selectively not toconduct when the memory cells are being read.
 10. The voltage readingenhancement system of claim 6 wherein the controller is responsive todirect the selective coupling device to recouple the cell plate in theactive sub-array to the corresponding cell plate in the referencesub-array when the active row signal is not received.
 11. The voltagereading enhancement system of claim 7 wherein the controller isresponsive to direct the second selective coupling device to recouplethe substrate in the active sub-array to the corresponding substrate inthe reference sub-array when the active row signal is not received. 12.A voltage reading enhancement system for an open digit line array DRAMdevice comprising a plurality of sub-arrays, the voltage readingenhancement system comprising: a selective coupling device selectivelyelectrically coupling a substrate of an active sub-array to acorresponding substrate of a reference sub-array; and a controllercoupled with the selective coupling device and operable to receive anactive row signal, the active row signal indicating an active row ofmemory cells within the active sub-array is to be coupled with an activedigit line, the controller being responsive to the active row signal todirect the selective coupling device to decouple the substrate in theactive sub-array from the corresponding substrate in the referencesub-array when the active row signal is received.
 13. The voltagereading enhancement system of claim 12 further comprising a secondselective coupling device selectively electrically coupling a cell plateof the active sub-array to a corresponding cell plate of the referencesub-array.
 14. The voltage reading enhancement system of claim 12wherein the selective coupling device is a transistor the controllerselectively causes to conduct when memory cells are not being read andselectively not to conduct when the memory cells are being read.
 15. Thevoltage reading enhancement system of claim 13 wherein the secondselective coupling device is a transistor the controller selectivelycauses to conduct when memory cells are not being read and selectivelynot to conduct when the memory cells are being read.
 16. The voltagereading enhancement system of claim 12 wherein the controller isresponsive to direct the selective coupling device to recouple thesubstrate in the active sub-array to the corresponding substrate in thereference sub-array when the active row signal is not received.
 17. Thevoltage reading enhancement system of claim 13 wherein the controller isresponsive to direct the second selective coupling device to recouplethe cell plate in the active sub-array to the corresponding cell platein the reference sub-array when the active row signal is not received.18. An open digit line array DRAM device comprising: a plurality ofsub-arrays of memory cells, the memory cells being disposed in rows andcolumns; a plurality of sense amplifiers disposed between thesub-arrays, each of the sense amplifiers receiving a first digit linefrom a column of memory cells in a first sub-array and second digit linefrom a column of memory cells in a second sub-array; a row addressingsystem operably connected to the DRAM device, the row addressing systemresponsive to a row address signal by accessing a row in the DRAM devicecorresponding to the row address signal; a refresh indicator signalingwhen a row of memory cells is to be refreshed; a row refreshing circuit,operably connected with the row addressing system, the DRAM cells, andthe refresh indicator, the row refreshing circuit directing a refresh ofat least one row of memory cells in response to the refresh indicatorsignaling a row of memory cells is to be refreshed; and a voltagereading enhancement system comprising: a selective coupling deviceselectively electrically coupling a component of an active sub-array toa corresponding component of a reference sub-array; and a controllercoupled with the selective coupling device and operable to receive anactive row signal, the active row signal indicating an active row ofmemory cells within the active sub-array is to be coupled with an activedigit line, the controller being responsive to the active row signal todirect the selective coupling device to decouple the component in theactive sub-array from the corresponding component in the referencesub-array when the active row signal is received.
 19. The open digitline array DRAM device of claim 18 wherein the component of the activesub-array comprises a cell plate of the active sub-array, and whereinthe corresponding component of the reference sub-array comprises a cellplate of the reference sub-array.
 20. The open digit line array DRAMdevice of claim 18 wherein the component of the active sub-arraycomprises a substrate of the active sub-array, and wherein thecorresponding component of the reference sub-array comprises a substrateof the reference sub-array.
 21. The open digit line array DRAM device ofclaim 18 wherein the selective coupling device is a transistor thecontroller selectively causes to conduct when memory cells are not beingread and selectively not to conduct when the memory cells are beingread.
 22. The open digit line array DRAM device of claim 18 wherein thecontroller is responsive to direct the selective coupling device torecouple the component in the active sub-array to the correspondingcomponent in the reference sub-array when the active row signal is notreceived.
 23. A memory system comprising: a memory controller; a memorybus operably coupled with the memory controller to communicate memorycommands from the memory controller and communicate memory outputsignals to the memory controller; and a plurality of open digit linearray DRAM device, each open digit line DRAM device comprising: aplurality of sub-arrays of memory cells, the memory cells being disposedin rows and columns; a plurality of sense amplifiers disposed betweenthe sub-arrays, each of the sense amplifiers receiving a first digitline from a column of memory cells in a first sub-array and second digitline from a column of memory cells in a second sub-array; a rowaddressing system operably connected to the DRAM device, the rowaddressing system responsive to a row address signal by accessing a rowin the DRAM device corresponding to the row address signal; a refreshindicator signaling when a row of memory cells is to be refreshed; a rowrefreshing circuit, operably connected with the row addressing system,the DRAM cells, and the refresh indicator, the row refreshing circuitdirecting a refresh of at least one row of memory cells in response tothe refresh indicator signaling a row of memory cells is to berefreshed; and a voltage reading enhancement system comprising: aselective coupling device selectively electrically coupling a componentof an active sub-array to a corresponding component of a referencesub-array; and a controller coupled with the selective coupling deviceand operable to receive an active row signal, the active row signalindicating an active row of memory cells within the active sub-array isto be coupled with an active digit line, the controller being responsiveto the active row signal to direct the selective coupling device todecouple the component in the active sub-array from the correspondingcomponent in the reference sub-array when the active row signal isreceived.
 24. The memory system of claim 23 wherein the component of theactive sub-array comprises a cell plate of the active sub-array, andwherein the corresponding component of the reference sub-array comprisesa cell plate of the reference sub-array.
 25. The memory system of claim23 wherein the component of the active sub-array comprises a substrateof the active sub-array, and wherein the corresponding component of thereference sub-array comprises a substrate of the reference sub-array.26. The memory system of claim 23 wherein the selective coupling deviceis a transistor the controller selectively causes to conduct when memorycells are not being read and selectively not to conduct when the memorycells are being read.
 27. The memory system of claim 23 wherein thecontroller is responsive to direct the selective coupling device torecouple the component in the active sub-array to the correspondingcomponent in the reference sub-array when the active row signal is notreceived.
 28. A computer system, comprising: a processor; an inputdevice, operably connected to the processor, allowing data to be enteredinto the computer system; an output device, operably connected to theprocessor, allowing data to be output from the computer system; and asystem memory operably connected to the processor through a system bus,the system memory comprising a plurality of open digit line array DRAMdevices having a plurality of rows of DRAM cells, the DRAM cellsreceiving, storing, and outputting data, the system memory comprising: amemory controller; a memory bus operably coupled with the memorycontroller to communicate memory commands from the memory controller andcommunicate memory output signals to the memory controller; and aplurality of open digit line array DRAM device, each open digit lineDRAM device comprising: a plurality of sub-arrays of memory cells, thememory cells being disposed in rows and columns; a plurality of senseamplifiers disposed between the sub-arrays, each of the sense amplifiersreceiving a first digit line from a column of memory cells in a firstsub-array and second digit line from a column of memory cells in asecond sub-array; a row addressing system operably connected to the DRAMdevice, the row addressing system responsive to a row address signal byaccessing a row in the DRAM device corresponding to the row addresssignal; a refresh indicator signaling when a row of memory cells is tobe refreshed; a row refreshing circuit, operably connected with the rowaddressing system, the DRAM cells, and the refresh indicator, the rowrefreshing circuit directing a refresh of at least one row of memorycells in response to the refresh indicator signaling a row of memorycells is to be refreshed; and a voltage reading enhancement systemcomprising: a selective coupling device selectively electricallycoupling a component of an active sub-array to a corresponding componentof a reference sub-array; and a controller coupled with the selectivecoupling device and operable to receive an active row signal, the activerow signal indicating an active row of memory cells within the activesub-array is to be coupled with an active digit line, the controllerbeing responsive to the active row signal to direct the selectivecoupling device to decouple the component in the active sub-array fromthe corresponding component in the reference sub-array when the activerow signal is received.
 29. The computer system of claim 28 wherein thecomponent of the active sub-array comprises a cell plate of the activesub-array, and wherein the corresponding component of the referencesub-array comprises a cell plate of the reference sub-array.
 30. Thecomputer system of claim 28 wherein the component of the activesub-array comprises a substrate of the active sub-array, and wherein thecorresponding component of the reference sub-array comprises a substrateof the reference sub-array.
 31. The computer system of claim 28 whereinthe selective coupling device is a transistor the controller selectivelycauses to conduct when memory cells are not being read and selectivelynot to conduct when the memory cells are being read.
 32. The computersystem of claim 28 wherein the controller is responsive to direct theselective coupling device to recouple the component in the activesub-array to the corresponding component in the reference sub-array whenthe active row signal is not received.
 33. A method for enhancing theaccuracy of reading stored memory cell voltages in an open digit linearray DRAM device, the method comprising: coupling a component of anactive sub-array to a corresponding component of a reference sub-array;and selectively decoupling the component of the active sub-array fromthe corresponding component of the reference sub-array when an activerow of memory cells within the active sub-array is to be connected to anactive digit line.
 34. The method of claim 33 wherein the component ofthe active sub-array comprises a cell plate of the active sub-array, andwherein the corresponding component of the reference sub-array comprisesa cell plate of the reference sub-array.
 35. The method of claim 33wherein the component of the active sub-array comprises a substrate ofthe active sub-array, and wherein the corresponding component of thereference sub-array comprises a substrate of the reference sub-array.36. The method of claim 33 wherein the component of the active sub-arrayis recoupled to the corresponding component of the reference sub-arraywhen an active row of memory cells within the active sub-array is not tobe connected to an active digit line.
 37. A method for enhancing theaccuracy of reading stored memory cell voltages in an open digit linearray DRAM device, the method comprising: coupling a cell plate of anactive sub-array to a corresponding cell plate of a reference sub-array;and selectively decoupling the cell-plate of the active sub-array fromthe corresponding cell plate of the reference sub-array when an activerow of memory cells within the active sub-array is to be connected to anactive digit line.
 38. The method of claim 37 further comprisingcoupling a substrate of the active sub-array to a correspondingsubstrate of the reference sub-array.
 39. The method of claim 37 whereinthe cell plate of the active sub-array is recoupled to the correspondingcell plate of the reference sub-array when an active row of memory cellswithin the active sub-array is not to be connected to an active digitline.
 40. The method of claim 38 wherein the substrate of the activesub-array is recoupled to the corresponding substrate of the referencesub-array when an active row of memory cells within the active sub-arrayis not to be connected to an active digit line.
 41. A method forenhancing the accuracy of reading stored memory cell voltages in an opendigit line array DRAM device, the method comprising: coupling asubstrate of an active sub-array to a corresponding substrate of areference sub-array; and selectively decoupling the substrate of theactive sub-array from the corresponding substrate of the referencesub-array when an active row of memory cells within the active sub-arrayis to be connected to an active digit line.
 42. The method of claim 41further comprising coupling a cell plate of the active sub-array to acorresponding substrate of the reference sub-array.
 43. The method ofclaim 41 wherein the substrate of the active sub-array is recoupled tothe corresponding substrate of the reference sub-array when an activerow of memory cells within the active sub-array is not to be connectedto an active digit line.
 44. The method of claim 42 wherein the cellplate of the active sub-array is recoupled to the corresponding cellplate of the reference sub-array when an active row of memory cellswithin the active sub-array is not to be connected to an active digitline.